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FEATURES 35 MSPS Encode Rate 16 pF Input Capacitance 550 mW Power Dissipation Industry-Standard Pinouts MIL-STD-883 Compliant Versions Available APPLICATIONS Professional Video Systems Special Effects Generators Electro-Optics Digital Radio Electronic Warfare (ECM, ECCM, ESM)
NLINV 12 NMINV 28 VIN 23 RT 18
Monolithic 8-Bit Video A/D Converter AD9048
FUNCTIONAL BLOCK DIAGRAM
AD9048
1 R 2 R 127 R/2 RM 27 R/2 128 E N C O D I N G L O G I C
1 2 3
D1 (MSB) D2 D3 D3 D5 D6 D7 D8 (LSB)
L A T C H
4 13 14 15 16
R R
254
GENERAL DESCRIPTION
RB 26 CONVERT 17
6 10 7 8
255
The AD9048 is an 8-bit, 35 MSPS flash converter, made on a high speed bipolar process, which is an alternate source for the TDC1048 unit, and offers enhancements over its predecessor. Lower power dissipation makes the AD9048 attractive for a variety of system designs. Because of its wide bandwidth, it is an ideal choice for real-time conversion of video signals. Input bandwidth is flat with no missing codes. Clocked latching comparators, encoding logic, and output buffer registers operating at minimum rates of 35 MSPS preclude a need for a sample-and-hold (S/H) or track-and-hold (T/H) in most system designs using the AD9048. All digital control inputs and outputs are TTL compatible. Devices operating over two ambient temperature ranges and with two grades of linearity are available. Linearities of either 0.5 LSB or 0.75 LSB can be ordered for a commercial range of 0C to 70C or extended case temperatures of -55C to +125C.
9
5
11
19
25
VCC
VEE
DGND
AGND
Commercial versions are packaged in 28-lead DIPs; extended temperature versions are available in ceramic DIP and ceramic LCC packages. Both commercial units and MIL-STD-883 units are standard products. The AD9048 A/D converter is available in versions compliant with MIL-STD-883. Refer to the Analog Devices Military Products Databook or current AD9048/883B data sheet for detailed specifications.
REV. F
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) 2003 Analog Devices, Inc. All rights reserved.
AD9048-SPECIFICATIONS (typical with nominal supplies, unless otherwise noted.)
ABSOLUTE MAXIMUM RATINGS 1
VCC to DGND . . . . . . . . . . . . . . . . . -0.5 V DC to +7.0 V DC AGND to DGND . . . . . . . . . . . . . . -0.5 V DC to +0.5 V DC VEE to AGND . . . . . . . . . . . . . . . . . +0.5 V DC to -7.0 V DC VIN, VRT, or VRB to AGND . . . . . . . . . . . . . . . . . 0.5 V to VEE VRT to VRB . . . . . . . . . . . . . . . . . . . . -2.2 V DC to +2.2 V DC CONV, NMINV or NLINV to DGND-0.5 V DC to +5.5 V DC Applied Output Voltage to DGND -0.5 V DC to +5.5 V DC2 Applied Output Current, Externally Forced . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0 mA to +6.0 mA3, 4
Output Short-Circuit Duration . . . . . . . . . . . . . . . . . 1.0 sec5 Operating Temperature Range (Ambient) AD9048JJ/KJ/JQ/KQ . . . . . . . . . . . . . . . . . . . . 0C to 70C AD9048SE/SQ/TE/TQ . . . . . . . . . . . . . . -55C to +125C Maximum Junction Temperature (Plastic) . . . . . . . . . 150C6 Maximum Junction Temperature (Hermetic) . . . . . . . 150C6 Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . 300C Storage Temperature Range . . . . . . . . . . . . -65C to +150C
ELECTRICAL CHARACTERISTICS (V
Parameter (Conditions) RESOLUTION DC ACCURACY Differential Nonlinearity Integral Nonlinearity No Missing Codes INITIAL OFFSET ERROR Top of Reference Ladder Bottom of Reference Ladder Offset Drift Coefficient ANALOG INPUT Input Voltage Range Input Bias Current7 Input Resistance Input Capacitance Full Power Bandwidth8 REFERENCE INPUT Positive Reference Voltage9 Negative Reference Voltage9 Differential Reference Voltage Reference Ladder Resistance Ladder Temperature Coefficient Reference Ladder Current Reference Input Bandwidth DYNAMIC PERFORMANCE10 Conversion Rate Aperture Delay Aperture Uncertainty (Jitter) Output Delay (tPD) Output Hold Time (tOH)11 Transient Response12 Overvoltage Recovery Time13 Rise Time Fall Time Output Time Skew14 NMINV and NLINV INPUTS 0.4 V Input Current 2.4 V Input Current 5.5 V Input Current CONVERT INPUT Logic "1" Voltage Logic "0" Voltage Logic "1" Current Logic "0" Current Input Capacitance Convert Pulsewidth (LOW) Convert Pulsewidth (HIGH) 25C Full 25C Full Full 25C Full 25C Full Full Full 25C Full 25C Full 25C 25C Full Full Full Full Full Full 25C 25C 25C 25C 25C 25C 25C 25C 25C 25C 25C Full Full Full Full Full Full Full 25C 25C 25C I VI I VI VI I VI I VI V V I VI I VI IV IV V V V VI V VI V I IV IV I I IV V I I I VI VI VI VI VI VI VI IV I I Temp Test Level
CC
= +5.0 V; VEE = -5.2 V; Differential Reference Voltage = 2.0 V, unless otherwise noted.)
AD9048KJ/KQ Min Typ Max 8 0.4 0.6 0.75 1.0 0.75 1.0 0.3 0.4 Guaranteed 12 12 8 8 5 4 20 -2.1; +0.1 36 60 100 300 16 15 20 10 12 12 8 8 0.5 0.75 0.5 0.75 AD9048SE/SQ Min Typ Max 8 0.4 0.6 Guaranteed 5 4 20 -2.1; +0.1 36 60 100 300 16 15 0.0 -2.0 2.0 60 0.22 23 10 38 2.4 25 9 8 6 8 4.5 20 10 12 12 8 8 0.75 1.0 0.75 1.0 AD9048TE/TQ Min Typ Max 8 0.3 0.4 Guaranteed 5 4 20 -2.1; +0.1 36 60 100 300 16 15 20 12 12 8 8 mV mV mV mV V/C 0.5 0.75 0.5 0.75 Unit Bits LSB LSB LSB LSB
AD9048JJ/JQ Min Typ Max 8
Guaranteed 5 4 20 -2.1; +0.1 36 60 100 300 16 15 0.0 -2.0 2.0 60 0.22 23 10 38 2.4 25 13 8 6 8 4.5 20
200 40 10
200 40 10
200 40
200 40
V A A k k pF MHz V V V /C mA MHz MHz ns ps ns ns ns ns ns ns ns A A A V V A A pF ns ns
30
125 40
30
0.0 -2.0 2.0 60 125 0.22 23 40 10 38 2.4 25 9 8 6 8 4.5
30
125 40
30
0.0 -2.0 2.0 60 125 0.22 23 40 10 38 2.4 25 9 8 6 8 4.5
35
35 5 50 15 5 20 9 14 7 200 150 150
35 5 50 15 5 20 9 14 7 200 150 150
35 5 50 15 5 20 9 14 7 200 150 150
5 50 15 20 9 14 7 200 150 150
5
2.0 0.8 150 500 6
2.0 0.8 150 500 6
2.0 0.8 150 500 6
2.0 0.8 150 500 6
4 18 10
4 18 10
4 18 10
4 18 10
-2-
REV. F
AD9048
Parameter (Conditions) AC LINEARITY In-Band Harmonics DC to 2.438 MHz15 DC to 9.35 MHz16 Signal-to-Noise Ratio (SNR)15 1.248 MHz Input Frequency17 2.438 MHz Input Frequency17 1.248 MHz Input Frequency18 2.438 MHz Input Frequency18 Signal-to-Noise Ratio (SNR)16 1.248 MHz Input Frequency17 9.35 MHz Input Frequency17 Noise Power Ratio (NPR)19 Differential Phase 20 Differential Gain 20 DIGITAL OUTPUTS Logic "1" Voltage Logic "0" Voltage Short Circuit Current5 POWER SUPPLY Positive Supply Current Negative Supply Current Nominal Power Dissipation Reference Ladder Dissipation Temp Test Level AD9048JJ/JQ Min Typ Max AD9048KJ/KQ Min Typ Max AD9048SE/SQ Min Typ Max AD9048TE/TQ Min Typ Max Unit
25C 25C 25C 25C 25C 25C 25C 25C 25C 25C 25C Full Full Full 25C Full 25C Full 25C 25C
I V I I I I I V IV IV IV VI VI VI I VI I VI V V
47 43.5 43 52.5 52
50 48 44 44 53 53
49 45 44 54 53 45 36.5 1 2
55 48 46 46 55 55 46 40.5 39 1 2
47 43.5 43 52.5 52 43.5 36.5
50 48 44 44 53 53 44 40.5 39 1 2
49 45 44 54 53 45
55 48 46 46 55 55
dBc dBc dB dB dB dB dB dB dB Degree % V V mA mA mA mA mA mW mW
43.5 44 40.5 36.5 39
46 40.5 36.5 39 1 2 2.4
2.4 0.5 30 34 90 550 45 56 58 110 120
2.4 0.5 30 34 90 550 45
10 11
2.4 0.5 30 34 90 550 45 56 58 110 120
0.5 30 34 90 550 45 56 58 110 120
56 58 110 120
NOTES 1 Maximum ratings are limiting values to be applied individually, and beyond which the serviceability of the device may be impaired. Functional operation under any of these conditions is not necessarily implied. Exposure to absolute maximum rating conditions for extended periods of time may affect device reliability. 2 Applied voltage must be current-limited to specified range. 3 Forcing voltage must be limited to specified range. 4 Current is specified as negative when flowing into the device. 5 Output High; one pin to ground; 1s duration. 6 Typical thermal impedances (no air flow) are as follows: Ceramic DIP: JA = 49C/W, JC = 15C/W; LCC: JA = 69C/W, JC = 21C/W; JLCC: JA = 59C/W; JC = 19C/W. To calculate junction temperature (T J), use power dissipation (PD) and thermal impedance: T J = PD (JA) + TAMBIENT = PD (JC) = + TCASE. 7 Measured with V IN = 0 V and CONVERT low (sampling mode). 8 Determined by beat frequency testing for no missing codes. 9 VRT VRB under all circumstances.
Outputs terminated with 40 pF and eight 10 pull-up resistors. Interval from 50% point of leading edge CONVERT pulse to change in output data. 12 For full-scale step input, 8-bit accuracy attained in specified time. 13 Recovers to 8-bit accuracy in specified time after -3 V input overvoltage. 14 Output time skew includes high-to-low and low-to-high transitions as well as bit-to-bit time skew differences. 15 Measured at 20 MHz encode rate with analog input 1 dB below full scale. 16 Measured at 35 MHz encode rate with analog input 1 dB below full scale. 17 RMS signal to rms noise. 18 Peak signal to rms noise. 19 DC to 8 MHz noise bandwidth with 1.248 MHz slot; four sigma loading; 20 MHz encode. 20 Clock frequency = 4 x NTSC = 14.32 MHz. Measured with 40-IRE modulated ramp. Specifications subject to change without notice.
EXPLANATION OF TEST LEVELS
Test Level I - 100% production tested. Test Level II - 100% production tested at 25C and sample tested at specific temperatures. Test Level III - Sample tested only. Test Level IV - Parameter is guaranteed by design and characterization testing. Test Level V - Parameter is a typical value only. Test Level VI - All devices are 100% production tested at 25C. 100% production tested at temperature extremes for military temperature devices; sample tested at temperature extremes for commercial/industrial devices.
REV. F
-3-
AD9048
ORDERING GUIDE PIN CONFIGURATIONS
Model AD9048JJ AD9048KJ AD9048JQ AD9048KQ AD9048SE/833B2 AD9048TE/833B2 AD9048SQ/833B2 AD9048TQ/833B2
Linearity 0.75 LSB 0.5 LSB 0.75 LSB 0.5 LSB 0.75 LSB 0.5 LSB 0.75 LSB 0.5 LSB
Temperature 0C to 70C 0C to 70C 0C to 70C 0C to 70C -55C to +125C -55C to +125C -55C to +125C -55C to +125C
Package Option1 J-28A J-28A D-28 D-28 E-28A E-28A D-28 D-28
DIP (D Package)
(MSB) D1 1 D2 2 D3 3 D4 4 DGND 5 VCC 6 VEE 7 VEE 8 VEE 9 VCC 10 DGND 11 NLINV 12 D5 13 D6 14
28 NMINV 27 RM 26 RB 25 AGND
AD9048
TOP VIEW
(Not to Scale)
24 NC 23 VIN 22 NC 21 NC 20 NC 19 AGND 18 RT 17 CONVERT 16 D8 (LSB) 15 D7
NOTES 1 E = Leadless Ceramic Chip Carrier; J = J-Leaded Ceramic; D = Cerdip. 2 MIL-STD-883 and Standard Military Drawing available.
MECHANICAL INFORMATION
NC = NO CONNECT
Die Dimensions . . . . . 140 mils x 137 mils x 21 mils ( 2) mils Pad Dimensions . . . . . . . . . . . . . . . . . . . . . . . . 4 mils x 4 mils Metallization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gold Backing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . None Substrate Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VEE Passivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Nitride Die Attach . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gold Eutectic Bond Wire . . . . . . . . . . . . . . . 1 mils Gold; Gold Ball Bonding
LCC (E Package)
D1 (MSB) NMINV RM D4 D3 D2 RB
4
3
2
1
28 27 26
DGND 5 VCC 6 VEE 7 VEE 8 VEE 9 VCC 10 DGND 11
25 24
AGND NC VIN NC NC NC AGND
AD9048
TOP VIEW (Not to Scale)
23 22 21 20 19
AGND
AIN
AGND
12 13 14 15 16 17 18
(LSB) D8
NC
D7
RLOW RMID NMINV MSB D2 D3 D4
RTOP
CONV D8 D7 D6 D5 NLINV
RB 26 RM 27 NMINV 28 (MSB) D1 1 D2 2 D3 3 D4 4
NC = NO CONNECT
J-Leaded Ceramic (J Package)
AGND AGND
19 18 17
VIN
NC
25 24 23 22 21 20
NC
NC
CONVERT
NLINV D5
D6
RT
RT CONVERT D8 (LSB) D7 D6 D5 NLINV
16 15 14 13 12
DGND
DGND
AD9048
(Not to Scale) (Not to Scale)
TOP VIEW TOP VIEW
VCC VCC
VEE VEE VEE
VCC VCC DGND
Figure 1. Bonding Diagram
5
6
7
8
9
10 11
DGND
NC = NO CONNECT
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9048 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
-4-
DGND
VEE
VEE
VCC
VEE
VCC
REV. F
AD9048
PIN FUNCTION DESCRIPTIONS
Mnemonic D1-D8
Description Eight Digital Outputs. D1 (MSB) is the most significant bit of the digital output word; D8 (LSB) is the least significant bit. One of Two Analog Ground Returns. Both grounds should be connected together and to low impedance ground plane near the AD9048. One of Two Digital Ground Returns. Both grounds should be connected together and to low impedance ground plane near the AD9048. Positive Supply Terminals; Nominally 5.0 V Negative Supply Terminals; Nominally -5.2 V Input for Conversion Signal. Sample of analog input signal taken on rising edge of this pulse.
Mnemonic RB RM RT VIN NMINV
Description Most Negative Reference Voltage for Internal Reference Ladder Midpoint Tap on Internal Reference Ladder Most Positive Reference Voltage for Internal Reference Ladder Analog Input Signal Pin "Not Most Significant Bit Invert." In normal operation, this pin floats high; logic LOW at NMINV inverts most significant bit of digital output word [D1 (MSB)]. "Not Least Significant Bit Invert." In normal operation, this pin floats high; logic LOW at NLINV inverts the seven least significant bits of the digital output word.
AGND
DGND
VCC VEE CONVERT
NLINV
-5.2V 0.1 F
+5.0V 0.1 F
VEE 100 AD1 VIN 510 AD2 CONVERT
VCC (MSB) D1 D2 D3 D4
AD9048
-2.0V RB
D5 D6 D7
RT DIGITAL GROUND ALL RESISTORS 5% ALL CAPACITORS 20% ALL SUPPLY VOLTAGES 5%
(LSB) D8 ANALOG GROUND 1k LOAD RESISTORS
OPTION #1 (STATIC): AD1 = -2.0V; AD2 = +2.4V OPTION #2 (DYNAMIC): SEE WAVEFORMS 0V
AD1 640 s
-2.0V
AD2 5s
VIH VIL
Figure 2. Burn-In Diagram
REV. F
-5-
AD9048
THEORY OF OPERATION
Refer to the Functional Block Diagram of the AD9048. The AD9048 comprises three functional sections: a comparator array, encoding logic, and output latches. Within the array, the analog input signal to be digitized is compared with 255 reference voltages. The outputs of all comparators whose references are below the input signal level will be high; outputs whose references are above that level will be low. The n-of-255 code that results from this comparison is applied to the encoding logic where it is converted into binary coding. When it is inverted with dc signals applied to the NLINV and/or NMINV pins, it becomes twos complement. After encoding, the signal is applied to the output latch circuits where it is held constant between updates controlled by the application of CONVERT pulses. The AD9048 uses strobed latching comparators in which comparator outputs are either high or low, as dictated by the analog input level. Data appearing at the output pins have a pipeline delay of one encode cycle. Input signal levels between the references applied to RT (Pin 18) and RB (Pin 26) will appear at the output as binary numbers between 0 and 255, inclusive. Signals outside that range will show up as either full-scale positive or full-scale negative outputs. No damage will occur to the AD9048 as long as the input is within the voltage range of VEE to 0.5 V. The significantly reduced input capacitance of the AD9048 lowers the drive requirements of the input buffer/amplifier and also induces much smaller phase shift in the analog input signal. Applications that depend on controlled phase shift at the converter input can benefit from using the AD9048 because of its inherently lower phase shift. The CONVERT, analog input, and digital output circuits are shown in Figure 3.
5.0V 5.0V 13k
System timing, which provides details on delays through the AD9048 as well as the relationships of various timing events, is shown in Figure 4.
N+1 ANALOG INPUT N N+2 APERTURE DELAY CONVERT
tOH
OUTPUT DATA N-1 N DATA CHANGING N+1 DATA CHANGING
tPD
Figure 4. Timing Diagram
Dynamic performance of the AD9048, i.e., typical signal-tonoise ratio, is illustrated in Figures 5 and 6.
50
48
SIGNAL-TO-NOISE RATIO - dB SIGNAL-TO-NOISE RATIO - dB
46
44
42
40
38 100kHz 1MHz 10MHz ANALOG INPUT FREQUENCY - 1dB BELOW FULL-SCALE
Figure 5. Dynamic Performance (20 MHz Encode Rate)
50
48 CONVERT DIGITAL OUTPUTS
46
44
RT R
42
40 R/2 RM -5.2V ANALOG INPUT R -5.2V -5.2V COMPARATOR CELLS RB -5.2V R/2 38 100kHz 1MHz 10MHz ANALOG INPUT FREQUENCY - 1dB BELOW FULL-SCALE
Figure 6. Dynamic Performance (35 MHz Encode Rate)
Figure 3. Input/Output Circuits
-6-
REV. F
AD9048
LAYOUT SUGGESTIONS
0.1 F -5.2V
Designs that use the AD9048 or any other high speed device must follow some basic layout rules to ensure optimum performance. The first requirement is to have a large, low impedance ground plane under and around the converter. If the system uses separate analog and digital grounds, both should be solidly connected together, and to the ground plane, as closely to the AD9048 as practical to avoid ground loop currents. Ceramic 0.1 F decoupling capacitors should be placed as closely as possible to the supply pins of the AD9048. For decoupling low frequency signals, use 10 F tantalum capacitors also connected as closely as practical to voltage supply pins. Within the AD9048, reference currents may vary because of coupling between the clock and input signals. As a result, it is important that the ends of the reference ladder, RT (Pin 18) and RB (Pin 26), be connected to low impedances (as measured from ground). If the AD9048 is being used in a circuit in which the reference is not varied, a bypass capacitor to ground is strongly recommended. In applications that use varying references, they must be driven from a low impedance source.
ANALOG INPUT (0V TO 2V)
AD589
10k
2k
27 100
0.1 F
2N3906 5
AD741
1k R R 43 50 AD9617/AD9618, AD9620/AD9630, AD847 VIN 1k
0.1 F RB RT D1 (MSB)
AD9048
CONVERT VEE VCC 0.1 F -5.2V +5.0V
TTL CONVERT SIGNAL
D8 (LSB)
0.1 F
Figure 7. Typical Connections
Table I. Truth Table Binary Step Range -2.000 V FS 7.8431 mV Step 0.0000 V -0.0078 V * * * -0.9961 V -1.0039 V -1.0118 V * * * -1.9921 V -2.0000 V -2.0480 V FS 8.000 mV Step 0.0000 V -0.0080 V * * * -1.0160 V -1.0240 V -1.0320 V * * * -2.0320 V -2.0400 V True NMINV = 1 NLINV = 1 00000000 00000001 * * * 01111111 10000000 10000001 * * * 11111110 11111111 Inverted 0 0 11111111 11111110 * * * 10000000 01111111 01111110 * * * 00000001 00000000 True Offset Twos Complement Inverted 1 0 01111111 01111110 * * * 00000000 11111111 11111110 * * * 10000001 10000000
000 001 * * * 127 128 129 * * * 254 255
0 1 10000000 10000001 * * * 11111111 00000000 00000001 * * * 01111110 01111111
REV. F
-7-
AD9048
OUTLINE DIMENSIONS 28-Terminal Ceramic Leadless Chip Carrier [LCC] (E-28A)
Dimensions shown in inches and (millimeters)
0.300 (7.62) REF 0.075 (1.91) REF
19 18 26 25
28-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP] (D-28)
Dimensions shown in inches and (millimeters)
0.100 (2.54) 0.064 (1.63)
0.020 (0.51) MIN 0.028 (0.71) 0.022 (0.56)
0.005 (0.13) MIN
0.100 (2.54) MAX
28 15
0.458 (11.63) SQ 0.442 (11.23)
0.458 (11.63) MAX SQ
0.05 (1.27)
BOTTOM VIEW
28 1
0.610 (15.49) 0.580 (12.73)
0.075 (1.91) REF
11
0.15 (3.81) REF
4 5
PIN 1
1
14
12
0.088 (2.24) 0.054 (1.37)
0.055 (1.40) 0.045 (1.14)
0.095 (2.41) 0.075 (1.90)
0.085 (2.16) MAX
1.490 (37.85) MAX
0.060 (1.52) 0.015 (0.38) 0.150 (3.81) MIN SEATING PLANE
0.620 (15.75) 0.590 (14.99)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
0.200 (5.08) 0.125 (3.18)
0.018 (0.46) 0.008 (0.20)
0.026 (0.66) 0.014 (0.36)
0.100 (2.54)
0.070 (1.78) 0.030 (0.76)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
28-Lead Ceramic Chip Carrier - J-Formed Leads [JLCC] (J-28A)
Dimensions shown in inches and (millimeters)
0.125 (3.18) MAX
4 5 PIN 1
0.460 (11.68) SQ 0.440 (11.18)
26 25
0.040 (1.02) REF x 45 3 PLACES
25
0.020 (0.51) REF x 45
26 4 5 PIN 1 INDEX 0.055 (1.40)
0.035 (0.89) 0.025 (0.64) 0.450 (11.43) 0.410 (10.41) 0.022 (0.56) 0.012 (0.30) 0.050 (1.27)
TOP VIEW
0.310 (7.87) 0.290 (7.37)
BOTTOM VIEW
11 12 18
19
19 18 12
11
0.500 (12.70) SQ 0.480 (12.19) CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETERS DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
Revision History
Location 5/03--Data Sheet changed from REV. E to REV. F. Page
Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Changes to OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
09/01--Data Sheet changed from REV. D to REV. E.
Change in ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
05/01--Data Sheet changed from REV. C to REV. D.
Change in ORDERING GUIDE and PIN DESIGNATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Edits to 28-Lead Ceramic Side-Brazed DIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 -8- REV. F
C00555-0-5/03(F)
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